1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, the present invention relates to a phase change memory devices.
A claim of priority is made to Korean Patent Application No. 10-2005-0083581, filed on Sep. 8, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
A phase-change random access memory (PRAM), also known as an Ovonic Unified Memory (OUM), includes a phase-change material such as a chalcogenide alloy which is responsive to energy (e.g., thermal energy) so as to be stably transformed between crystalline and amorphous states. Such a PRAM is disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase-change material of the PRAM exhibits a relatively low resistance in its crystalline state, and a relatively high resistance in its amorphous state. In conventional nomenclature, the low-resistance crystalline state is referred to as a ‘set’ state and is designated logic “0”, while the high-resistance amorphous state is referred to as a ‘reset’ state and is designated logic “1”.
The terms “crystalline” and “amorphous” are relative terms in the context of phase-change materials. That is, when a phase-change memory cell is said to be in its crystalline state, one skilled in the art will understand that the phase-change material of the cell has a more well-ordered crystalline structure when compared to its amorphous state. A phase-change memory cell in its crystalline state need not be fully crystalline, and a phase-change memory cell in its amorphous state need not be fully amorphous.
Generally, the phase-change material of a PRAM is reset to an amorphous state by joule heating of the material in excess of its melting point temperature for a relatively short period of time. On the other hand, the phase-change material is set to a crystalline state by heating the material below its melting point temperature for a longer period of time. In each case, the material is allowed to cool to its original temperature after the heat treatment. Generally, however, the cooling occurs much more rapidly when the phase-change material is reset to its amorphous state.
The speed and stability of the phase-change characteristics of the phase-change material are critical to the performance characteristics of the PRAM. As suggested above, chalcogenide alloys have been found to have suitable phase-change characteristics, and in particular, a compound including germanium (Ge), antimony (Sb) and tellurium (Te) (e.g., Ge2Sb2Te5 or GST) exhibits a stable and high speed transformation between amorphous and crystalline states.
FIGS. 1A and 1B illustrate a memory cell 10 in a ‘set’ state and in a ‘reset’ state, respectively. In this example, the memory cell 10 includes a phase-change resistive element 11 and a diode D connected in series between a bit line BL and a word line WL. It should be noted that FIGS. 1A and 1B are general schematic views only, that the configuration of the phase-change resistive element 11 is presented as an example only, and that other configurations and connections with respect to the phase-change resistive element 11 are possible. As an example of one variation, the phase-change resistive element 11 may instead be connected in series with a transistor between the bit line BL and a reference potential, with the gate of the transistor connected to the word line WL.
In each of FIGS. 1A and 1B, the phase-change resistive element 11 includes a top electrode 12 formed on a phase-change material 14. In this example, the top electrode 12 is electrically connected to a bit line BL of a PRAM memory array (not shown). A conductive bottom electrode contact (BEC) 16 is formed between the phase-change material 14 and a conductive bottom electrode 18. The diode D is electrically connected between the bottom electrode 18 and the word line WL.
In FIG. 1A, the phase-change material 14 is illustrated as being in its crystalline state. As described previously, this means that the memory cell 10 is in a low-resistance ‘set’ state or logic 0 state. In FIG. 1B, a portion of the phase-change material 14 is illustrated as being amorphous. Again, this means that the memory cell 10 is in a high-resistance ‘reset’ state or logic 1 state.
The set and reset states of the memory cell 10 of FIGS. 1A and 1B are established by controlling the magnitude and duration of current flow through the BEC 16. That is, the phase-change resistive element 11 is activated (or accessed) by operation of diode D which is responsive to a voltage of the word line WL. When activated, the memory cell 10 is programmed according to the voltage of the bit line BL. The bit line BL voltage is controlled to establish a programming current which causes the BEC 16 to act as a resistive heater which selectively programs the phase-change material 14 in its ‘set’ and ‘reset’ states.
FIG. 2 is a circuit diagram of a memory array 200 including the diode-type phase change memory cells of FIGS. 1A and 1B.
Referring to FIG. 2, each phase change memory cell of the memory array 200 includes a phase change element 11 and a diode D connected in series between a bit line BL and a word line WL. In order to select a memory cell, a high level voltage is applied to the corresponding selected bit line BL and a low level voltage is applied to the corresponding selected word line WL. The non-selected bit lines BL receive a low level voltage, and the remaining non-selected word lines WL receive a high level voltage.
FIG. 3 is a circuit diagram of a conventional phase change memory device 300.
Referring to FIG. 3, the phase change memory device 300 includes a memory array 310, a memory array controller 320, a write driver 320, a write driver WD, a column decoder YD, a row decoder XD, and a sense amplifier SAU.
The memory array 310 includes a plurality of memory cells 10, each comprised of a phase change element GST and a diode D connected between a bit line BL and a word line WL.
Each bit line BL is selectively connected to a data line DL by a respective column selection transistors CSTR, and the data line DL is connected to a sense node NA. The column selection transistors CSTR operate under control of the column decoder YD, which in turn is responsive to a column address signal YADD.
The write driver WD writes data to the memory cells 10 in a write operation mode. An exemplary structure of the write driver WD is disclosed in Korean Patent Application No. 2004-45849, and a detailed description thereof is omitted for the sake of brevity.
The row decoder XD controls a voltage at node NC of each word line WL so as to select a word line WL of a selected memory cell 10 to or from which data will be written or read in response to a row address XADD. As mentioned above, a word line WL is selected by application of a low level voltage thereto. The non-selected word lines WL receive a high level voltage.
The column decoder YD controls a voltage of a node NB to which a gate of a column selection transistor CSTR is connected, thus connecting or disconnecting the memory cell 10 to or from the corresponding node NA.
The sense amplifier SAU senses the voltage of the node NA to measure a data value when a data read operation is performed. The sense amplifier SAU includes a sense amplifier circuit S/A, a bias transistor BTR connected between an input terminal of the sense amplifier circuit S/A and a sense amplifier supply voltage VSA, and a clamp transistor PTR connected between the node NA and the input terminal of the sense amplifier circuit S/A. A reference voltage VREF is applied to the other input terminal of the sense amplifier circuit S/A.
The sense amplifier supply voltage VSA may be equal to a supply voltage VCC for driving the write driver WD, the column decoder YD, and the row decoder XD, or may be different from the supply voltage VCC.
The bias transistor BTR is turned on by a bias voltage VBIAS in a standby mode to maintain the node NA at the sense amplifier supply voltage VSA. The clamp transistor PTR is turned on by a clamp voltage VCLAMP in a read operation mode to maintain the node NA at a clamp voltage VCLAMP.
In order to apply the supply voltage VCC to the bit lines of selected memory cells 10, the memory array controller 320 includes transistors TR2 which are turned on in response to a signal CE, and transistors TR1 which are turned on in response to a signal nPulse before a data read operation or a data write operation to ground the bit lines.
As shown in FIG. 3, the write driver WD, the column decoder YD, and the row decoder XD are driven by the supply voltage VCC.
However, in a write operation mode, the phase change memory device 300 must maintain high level voltages at the nodes NA, NB, and NC of FIG. 3 in order to ensure sufficient current to reliably induce a phase transformation of the phase change material each memory cell. On the other hand, it is necessary generate a relatively low drive voltage to reliably execute in a read operation mode, and to generate a low level voltage in a standby mode to minimize power consumption caused by leakage current in the standby mode. These differing voltage requirements can result in complicated circuit schemes and manufacturing processes.